A very thorough examination, thank you!
I wonder why the SCSI2SD suffers in sequential read performance? It seems like it shouldn't be the case...
Hi, I'm a little late to the party here, but the reason why SCSI2SD V6 has the read performance it has is largely attributable to its complete lack of read-ahead cache. The main microcontroller that powers the SCSI2SD V6 is an STM32F205 has _128 kilobytes of SRAM total_. Most Ultra160/Ultra320 SCSI drives have multiple megabytes of readahead cache (The ST3146707LW, chosen at random, has 8 megabytes of RAM. That's around 60,000 times more RAM. Off the top of my head, I have no idea what percentage of that program memory is occupied by the SCSI2SD V6 program, but presumably a significant portion of it, if not most of it, is continually in-use at any given time. Adding additional, external SRAM isn't possible, because there are nowhere near enough un-used pins on the microcontrollers.
Looking at the SCSI2SD V5, all variants of which are based on the Cypress PSoC 5LP (P/N CY8C5267AXI-LP051), which has a mere 32 kilobytes of SRAM, you see a similar limitation.
Of course, all of this could be solved by using a more powerful, more-expensive MCU with significantly more pins.