How does the O2 determine cache size?


New member
Aug 30, 2020
The Netherlands
This is something I've been wondering about since picking up my RM7000C CPU swap project again. As I'd be swapping the CPU as well as the PROM, I was wondering if the cache too could be swapped for pin compatible SRAMs of higher capacity.

Is the cache size a set variable in the bit stream coming from the PROM, or does the system/CPU simply enumerate the cache size itself by checking the ICs? Just wondering if anyone happens to know this piece of the puzzle!


Jul 23, 2020
Edinburgh, Scotland, UK.
AFAIK it's somehow coded in the PROM. The guy who originally started all the R7K/600 stuff said he'd talked to IBM about it, who told him that a 16MB L2 would be possible, running 50% faster, but it can't be done without the PROM source code, something SGI flatly refused to release (even with SGI people asking for the code to be made public).

About us

  • Silicon Graphics User Group (SGUG) is a community for users, developers, and admirers of Silicon Graphics (SGI) products. We aim to be a friendly hobbyist community for discussing all aspects of SGIs, including use, software development, the IRIX Operating System, and troubleshooting, as well as facilitating hardware exchange.

User Menu