How does the O2 determine cache size?


New member
Aug 30, 2020
The Netherlands
This is something I've been wondering about since picking up my RM7000C CPU swap project again. As I'd be swapping the CPU as well as the PROM, I was wondering if the cache too could be swapped for pin compatible SRAMs of higher capacity.

Is the cache size a set variable in the bit stream coming from the PROM, or does the system/CPU simply enumerate the cache size itself by checking the ICs? Just wondering if anyone happens to know this piece of the puzzle!

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